Performance Enhancement of Multiuser Time Reversal UWB Communication System

UWB communication is a recent research area for indoor propagation channels. Time Reversal (TR) communication in UWB has shown promising results for improving the system performance. In multiuser environment, the system performance is significantly degraded due to the interference among different users. TR reduces the interference caused by multiusers due to its spatial focusing property. The performance of a multiuser TR communication system is further improved if the TR filter is modified. In this paper, multiuser TR in UWB communication is investigated using simple TR filter and a modified TR filter with circular shift operation. The concept of circular shift in TR is analytically studied. Thereafter, the channel impulse responses (CIR) of a typical indoor laboratory environment are measured. The measured CIRs are used to analyze the received signal peak power and signal to interference ratio (SIR) with and without performing the circular shift operation in a multiuser environment

Time Reversal Technique for Ultra Wide-band and MIMO Communication Systems

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Time Domain Measurements for a Time Reversal SIMO System in Reverberation Chamber and in an Indoor Environment

International audienceTime domain measurements are conducted for ultra-wideband (UWB) signals in a reverberation chamber (RC) and in a typical indoor environment for a single input multiple output (SIMO) time reversal (TR) system. Different TR characteristics i.e. TR peak performance, TR focusing gain, average power increase, signal to side lobe ratio (SSR) and delay spread are analyzed and compared to that of a single input single output (SISO) TR system

Millimeter-Wave System for High Data Rate Indoor Communications

This paper presents the realization of a wireless Gigabit Ethernet communication system operating in the 60 GHz band. The system architecture uses a single carrier modulation. A differential encoded binary phase shift keying modulation and a differential demodulation scheme are adopted for the intermediate frequency blocks. The baseband blocks use Reed- Solomon RS (255, 239) coding and decoding for channel forward error correction (FEC). First results of bit error rate (BER) measurements at 875 Mbps, without channel coding, are presented for different antennas.Comment: 5 page

MIMO Hardware Simulator: Digital Block Design for 802.11ac Applications with TGn Channel Model Test

International audienceThis paper presents new frequency domain and time domain architectures for the digital block of a hardware simulator of MIMO propagation channels. This simulator can be used for 802.11ac applications. The hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment, thus making it possible to ensure the same test conditions in order to compare the performance of various equipments. After the description of the general characteristics of the hardware simulator, the new architectures of the digital block are presented and designed on a Xilinx Virtex-IV FPGA. Their accuracy and latency are analyzed. TGn channel model E tests are given in details. Lastly, results for all TGn channel models are presented

Solution ASF pour un simulateur matériel du canal de propagation MIMO hétérogène

National audienceUn simulateur matériel permet de reproduire un canal radio souhaité et de tester au laboratoire divers systèmes de radiocommunications. Le changement des environnements est nécessaire pour simuler le canal de propagation hétérogène d'une manière continue. Cet article présente un simulateur matériel pour un scénario qui consiste à suivre une personne qui utilise le WLAN 802.11ac et se déplace d'abord d'un environnement bureautique vers un environnement indoor moyen, puis indoor large. Les réponses impulsionnelles du canal peuvent être obtenues à l'aide d'un sondeur de canal MIMO. Cependant, dans cet article, nous utilisons les modèles de canal TGn standardisés. L'architecture proposée est mise en oeuvre sur un FPGA Virtex-IV. La précision, le taux d'occupation sur le FPGA et la latence de cette architecture sont analysées. Une solution d'amélioration de la précision basée sur un facteur d'échelle automatique (Auto-Scale Factor : ASF) est également présentée

MIMO Hardware Simulator: Time Domain Versus Frequency Domain Architectures

19 pagesInternational audienceA hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment. This paper presents an overview of the digital block architectures of Multiple-Input Multiple-Output (MIMO) hardware simulators. First, the simple frequency architecture is presented and analyzed. Then, an improved frequency architecture, which works for streaming mode input signals, is considered. After, the time domain architecture is described and analyzed. The architectures of the digital block are presented and designed on a Xilinx Virtex-IV Field Programmable Gate Array (FPGA). Their accuracy, occupation on the FPGA and latencies are analyzed using Wireless Local Area Networks (WLAN) 802.11ac and Long Term Evolution System (LTE) signals. The frequency and the time approaches are compared and discussed, for indoor (using TGn channel models) and outdoor (using 3GPP-LTE channel models) environments. It is shown that the time domain architecture present the best solution for the design of the architecture of the hardware simulator digital block. Finally, a 2×2 MIMO time domain architecture is described and simulated with input signal that respects the bandwidth of the considered standards

Hardware Simulator: Digital Block Design for Time- Varying MIMO Channels with TGn Model B Test

International audienceA hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment. Thus, it makes possible to ensure the same test conditions in order to compare the performance of various equipments. This paper presents new frequency domain and time domain architectures of the digital block of a hardware simulator of MIMO propagation channels. The two architectures are tested with WLAN 802.11ac standard, in indoor environment, using time-varying TGn 802.11n channel model B. After the description of the general characteristics of the hardware simulator, the new architectures of the digital block are presented and designed on a Xilinx Virtex-IV FPGA. Their accuracy and latency are analyzed

MIMO hardware simulator design for heterogeneous indoor environments using TGn channel models

10 pagesInternational audienceA wireless communication system can be tested either in actual conditions or by using a hardware simulator reproducing actual conditions. With a hardware simulator it is possible to freely simulate a desired type of a radio channel. This paper presents new frequency domain and time domain architectures for the digital block of a hardware simulator of Multiple-Input Multiple-Output (MIMO) propagation channels. This simulator can be used for Wireless Local Area Networks (WLAN) 802.11ac applications. It characterizes an indoor scenario using TGn channel models. After the description of the general characteristics of the hardware simulator, the new architectures of the digital block are presented and designed on a Xilinx Virtex-IV Field Programmable Gate Array (FPGA). Their accuracy, occupation on the FPGA and latency are analyzed

MIMO Hardware Simulator: New Digital Block Design in Frequency Domain for Streaming Signals

11 pagesInternational audienceThis paper presents a new frequency domain architecture for the digital block of a hardware simulator of MIMO propagation channels. This simulator can be used for LTE and WLAN IEEE 802.11ac applications, in indoor and outdoor environments. It accepts signals in streaming mode. A hardware simulator must reproduce the behavior of the radio propagation channel, thus making it possible to test "on table" the mobile radio equipments. The advantages are: low cost, short test duration, possibility to ensure the same test conditions in order to compare the performance of various equipments. After the presentation of the general characteristics of the hardware simulator, the new architecture of the digital block is presented and designed on a Xilinx Virtex-IV FPGA. It is tested with time-varying 3GPP TR 36.803 channel model EVA and TGn channel model E. Finally, its accuracy is analyzed